Selected Publications:
arXiv
1. Dancing along Battery: Enabling Transformer with Run-time Reconfigurability on Mobile Devices [arXiv avaiable soon]
Y. Song, W. Jiang, B. Li, P. Qi, Q. Zhuge, E. H.-M. Sha, S. Dasgupta, Y. Shi, and C. Ding
Accepted by Design Automation Conference (DAC), 2021
2021
2. A Co-Design Framework of Neural Networks and Quantum Circuits Towards Quantum Advantage
W. Jiang, J. Xiong, and Y. Shi
3. When Machine Learning Meets Quantum Computers: A Case Study
W. Jiang, J. Xiong, and Y. Shi
in Proc. of Asia and South Pacific Design Automation Conference (ASP-DAC), (invited paper) [arXiv];
2020
4. Achieving Full Parallelism in LSTM via a Unified Accelerator Design
X. Zhang, W. Jiang, J. Hu
IEEE International Conference on Computer Design (ICCD2020@Online), Oct. 2020.
(acceptance rate 62/221=28.1%)
(acceptance rate 62/221=28.1%)
5. Hardware Design and the Competency Awareness of a Neural Network
Y. Ding, W. Jiang, Q. Lou, J. Liu, J. Xiong, X. Sharon Hu, X. Xu, and Y. Shi,
Nature Electronics, Aug. 2020 (in print)
6. Standing on the Shoulders of Giants: Hardware and Neural Architecture Co-Search with Hot Start [arXiv]
W. Jiang, L. Yang, S. Dasgupta, J. Hu and Y. Shi
International Conference on Hardware/Software Co-design and System Synthesis CODE+ISSS) in ESWEEK'20
(acceptance rate 94/375=25.1%)
also appears at IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Virtaul Conference, Oct. 2020.
(acceptance rate 94/375=25.1%)
also appears at IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Virtaul Conference, Oct. 2020.
7. Device-Circuit-Architecture Co-Exploration for Computing-in-Memory Neural Accelerators [arXiv]
W. Jiang, Q. Lou, Z. Yan, L. Yang, J. Hu, X. S. Hu and Y. Shi
IEEE Transactions on Computers (TC), Accepted, 2020.
8. Hardware/Software Co-Exploration of Neural Architectures [arXiv]
W. Jiang, L. Yang, E. H.-M. Sha, Q. Zhuge, S. Gu, S. Dasgupta, Y. Shi and J. Hu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Accepted, 2020.
9. Co-Exploration of Neural Architectures and Heterogeneous ASIC Accelerator Designs Targeting Multiple Tasks [arXiv]
L. Yang, Z. Yan, M. Li, H. Kwon, L. Lai, T. Krishana, V. Chandra, W. Jiang, and Y. Shi
Design Automation Conference (DAC), 2020.
(acceptance rate 228/992=23.0%)
(acceptance rate 228/992=23.0%)
10. NASS: Optimizing Secure Inference via Neural Architecture Search [arXiv]
B. Song, W. Jiang, Q. Lu, Y. Shi and T. Sato
Proc. European Conference on Artificial Intelligence (ECAI), Santiago de Compostela, June. 2020.
(acceptance rate 365/1363=26.8%)
(acceptance rate 365/1363=26.8%)
11. Co-Exploring Neural Architecture and Network-on-Chip Design for Real-Time Artificial Intelligence (BEST PAPER NOMINATION)
L. Yang*, W. Jiang*, W. Liu, E. H.-M. Sha, Y. Shi and J. Hu
Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), Beijing, Jan. 2020.
(acceptance rate 86/263=32.6%; * equal contribution)
(acceptance rate 86/263=32.6%; * equal contribution)
2019
12. Achieving Super-Linear Speedup across Multi-FPGA for Real-Time DNN Inference [arXiv] (BEST PAPER NOMINATION)
W. Jiang, E. H.-M. Sha, X. Zhang, L. Yang, Q. Zhuge, Y. Shi and J. Hu
International Conference on Hardware/Software Co-design and System Synthesis CODE+ISSS) in ESWEEK'19
(acceptance rate 66/243=27.2%)
also appears at ACM Transactions on Embedded Computing Systems (TECS), NYC, New York, USA, Oct. 2019.
(acceptance rate 66/243=27.2%)
also appears at ACM Transactions on Embedded Computing Systems (TECS), NYC, New York, USA, Oct. 2019.
13. Integrating Memristors and CMOS for Better AI
W. Jiang, B. Xie, C-C Liu and Y. Shi,
Nature Electronics (News and Views), Sep. 2019
14. When Neural Architecture Search Meets Hardware Implementation: from Hardware Awareness to Co-Design (Invited paper)
X. Zhang, W. Jiang, Y. Shi and J. Hu,
Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Miami, Florida, USA, Aug. 2019.
15. On Neural Architecture Search for Resource-Constrained Hardware Platforms (Invited paper)
Q. Lu, W. Jiang, X. Xiao, J. Hu and Y. Shi,
Proc. IEEE/ACM International Conference On Computer-Aided Design (ICCAD), Westminster, CO, 2019.
16. Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture Search [arXiv]
(BEST PAPER NOMINATION)
(BEST PAPER NOMINATION)
W. Jiang, X. Zhang, E. H.-M. Sha, L. Yang, Q. Zhuge, Y. Shi, and J. Hu
Design Automation Conference (DAC), 2019.
(acceptance rate 204/815=25%)
(acceptance rate 204/815=25%)
2018
17. Heterogeneous FPGA-based Cost-Optimal Design for Timing-Constrained CNNs
W. Jiang, E. H.-M. Sha, Q. Zhuge, L. Yang, X. Chen, and J. Hu
International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) in ESWEEK'18
(acceptance rate 67/270=24.8%)
also appear at IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Torino, Italy, Oct. 2018.
(acceptance rate 67/270=24.8%)
also appear at IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Torino, Italy, Oct. 2018.
18. On the Design of Time-Constrained and Buffer-Optimal Self-Timed Pipelines
W. Jiang, E. H.-M. Sha, Q. Zhuge, L. Yang, X. Chen, and J. Hu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Accepted, 2018.
19. Thermal-aware Task Mapping on Dynamically Reconfigurable Network-on-Chip based Multiprocessor System-on-Chip
W. Liu, L. Yang, W. Jiang, L. Feng, N. Guan, W. Zhang, and N. Dutt
IEEE Transactions on Computers (TC), Accepted, 2018.
20. Towards the Design of Efficient and Consistent Index Structure with Minimal Write Activities for Non-Volatile Memory
E. H.-M. Sha, W. Jiang, H. Dong, Z. Ma, R. Zhang, X. Chen and Q. Zhuge
IEEE Transactions on Computers (TC), 67(3), 432-448, 2018.
21. Efficient wear leveling for inodes of file systems on persistent memories
X. Chen, E. H.-M. Sha, Y. Zeng, C. Yang, W. Jiang and Q. Zhuge
Proc. Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, Mar. 2018.
22. On the Design of Minimal-Cost Pipeline Systems Satisfying Hard/Soft Real-Time Constraints (BEST PAPER AWARD)
W. Jiang, E. H.-M. Sha, Q. Zhuge, L. Yang, H. Dong and X. Chen
IEEE International Conference on Computer Design (ICCD2017@BOSTON)
(acceptance rate 75/258=29.1%)
also appear at IEEE Transactions on Emerging Topics in Computing (TETC), Jan. 2018.
(acceptance rate 75/258=29.1%)
also appear at IEEE Transactions on Emerging Topics in Computing (TETC), Jan. 2018.
2017
23. Work In Progress: Communication Optimization for Thermal Reliable Many-core Systems
W. Liu, L. Yang, W. Jiang and N. Guan
Proc. International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS), Seoul, South Korea, Oct. 2017.
24. Optimal Functional Unit Assignment and Voltage Selection for Pipelined MPSoC with Guaranteed Probability on Time Performance
W. Jiang, E. H.-M. Sha, Q. Zhuge, H. Dong and X. Chen
Proc. Languages, Compilers, and Tools for Embedded Systems (LCTES), Barcelona, Spain, Jun. 2017.
(acceptance rate 13/51=25.5%)
(acceptance rate 13/51=25.5%)
25. Efficient Assignment Algorithms to Minimize Operation Cost for Supply Chain Networks in Agile Manufacturing
W. Jiang, E. H.-M. Sha, Q. Zhuge and Lin Wu
Computers & Industrial Engineering (CAIE), Apr. 2017.
26. Synthesizing Distributed Pipelining Systems with Timing Constraints via Optimal Functional Unit Assignment and Communication Selection
W. Jiang, E. H.-M. Sha, X. Chen, L. Wu and Q. Zhuge
Journal of Computational Science (JOCS), Mar. 2017.
27. Optimal Functional-Unit Assignment for Heterogeneous Systems under Timing Constraint
W. Jiang, E. H.-M. Sha, X. Chen, L. Yang, L. Zhou and Q. Zhuge
IEEE Transactions on Parallel and Distributed Systems (TPDS), 28(9), 2567-2580, 2017.
28. FoToNoC: A Folded Torus-Like Network-on-Chip based Many-Core Systems-on-Chip in the Dark Silicon Era
L. Yang, W. Liu, W. Jiang, M. Li, P. Chen and E. H.-M. Sha
IEEE Transactions on Parallel and Distributed Systems (TPDS), 28(7), 1905-1918, 2017.
2016
29. Optimal Functional-Unit Assignment and Buffer Placement for Probabilistic Pipelines
W. Jiang , E. H.-M. Sha, Q. Zhuge and X. Chen
Proc. International Conference on Hardware/Software Co-design and System Synthesis (CODES+ISSS), Pittsburgh, PA, USA, Oct. 2016.
(acceptance rate 21/80=26.3%)
(acceptance rate 21/80=26.3%)
30. The Design of an Efficient Swap Mechanism for Hybrid DRAM-NVM Systems
X. Chen, E. H.-M. Sha, W. Jiang, Q. Zhuge, J. Chen, J. Qin, Y. Zeng
Proc. International Conference on Embedded Software (EMSOFT), Pittsburgh, PA, USA, Oct. 2016.
31. A New Design of In-Memory File System Based on File Virtual Address Framework
E. H.-M. Sha, X. Chen, Q. Zhuge, L. Shi and W. Jiang
IEEE Transactions on Computers (TC), 65(10), 2959-2972, Oct. 2016.
32. Application Mapping and Scheduling for Network-on-Chip-Based MPSoC With Fine-Grain Communication Optimization
L. Yang, W. Liu, W. Jiang, M. Li, J. Yi and E. H. M. Sha
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 24(10), 3027-3040, Oct. 2016.
33. Properties of Self-Timed Ring Architectures for Deadlock-Free and Consistent Configuration Reaching Maximum Throughput
W. Jiang, Q. Zhuge, X. Chen, L. Yang, J. Yi and E. H.-M. Sha
Journal of Signal Processing Systems (JSPS), 84(1), 123-137, Jul. 2016.
34. Optimal Functional Assignment and Communication Selection under Timing Constraint for Self-Timed Pipelines
W. Jiang, E. H.-M. Sha, X. Chen, Q. Zhuge and L. Wu
Proc. International Conference on Embedded Software and Systems (ICESS), Chengdu, China, Aug. 2016.
35. Efficient data placement for improving data access performance on domain-wall memory''
X. Chen, E. H.-M. Sha, Q. Zhuge, C. J. Xue, W. Jiang and Y. Wang
IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 24(10), 3094-3104, 2016.
36. FoToNoC: A hierarchical management strategy based on folded lorus-like Network-on-Chip for dark silicon many-core systems
(BEST PAPER NOMINATION)
(BEST PAPER NOMINATION)
L. Yang, W. Liu, W. Jiang , M. Li, J. Yi and E. H.-M. Sha
Proc. 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), Macao, Jan. 2016.
2015
37. Prevent Deadlock and Remove Blocking for Self-Timed Systems
E. H.-M. Sha, W. Jiang, Q. Zhuge, X. Chen and L. Yang
Proc. International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP), Zhangjiajie, China, Nov. 2015.
38. Optimizing data placement for reducing shift operations on domain wall memories
X. Chen, E. H.-M. Sha, Q. Zhuge, P. Dai and W. Jiang
Proc. Design Automation Conference (DAC), San Francisco, California, USA, Jun. 2015.
39. On the Design of High-Performance and Energy-Efficient Probabilistic Self-Timed Systems
E. H.-M. Sha, W. Jiang, Q. Zhuge, L. Yang and X. Chen
Proc. High Performance Computing and Communications (HPCC), NewYork, NY, USA, Aug. 2015.
40. Designing an Efficient Persistent In-Memory File System (BEST PAPER AWARD)
E. H.-M. Sha, X. Chen, Q. Zhuge, L. Shi and W. Jiang
Proc. the 4th IEEE Non-Volatile Memory System and Applications Symposium (NVMSA), Hongkong, Aug. 2015.
2014
41. On self-timed ring for consistent mapping and maximum throughput
W. Jiang, Q. Zhuge, J. Yi, L. Yang and E. H.-M. Sha
Proc. Embedded and Real-Time Computing Systems and Applications (RTCSA), Chongqing, China, Aug. 2014.
